A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Ramana Rao, K. V.
- Performance Evaluation of Capsicum Crop in Open Field and under Covered Cultivation
Authors
1 Precision Farming Development Centre,central Institute of Agricultural Engineering, Bhopal, M.P., IN
Source
International Journal of Agricultural Sciences, Vol 9, No 2 (2013), Pagination: 602-604Abstract
The performance of capsicum crop in open field and under covered cultivation was evaluated at Precision Farming Development Centre experimental field at Bhopal during December, 2011 to May, 2012. Under covered cultivation, black colour shade net having 50% shade factor was used in the study. Same crop cultural practices in the open field and under covered cultivation were adopted for comparison. Drip irrigation system was adopted in both the cases and irrigation system parameters such as frequency of irrigation and wetting pattern were collected. Other parameters such as soil temperature, duration of the crop, morphological parameters of the crop and yield were monitored. The study revealed that under shade net the crop yield was increased by 80 per cent over open field cultivation along with water saving of about 40 per cent in covered cultivation. The wetting pattern from the emitting device of 2 lph indicated maximum spread of 40 cm from emitter in case of crop under covered cultivation where as in open field the spread was 25 cm. Duration of the crop was also extended by 40 more days under covered cultivation.Keywords
Open Field, Covered Cultivation, Shade Net, Shade Factor, Micro Irrigation System, Capsicum Crop- Particle Swarm Optimization Approach for MST Problem in VLSI Routing
Authors
1 Pydah College of Engineering and Technology, Visakhapatnam, IN
Source
Programmable Device Circuits and Systems, Vol 5, No 5 (2013), Pagination: 225-227Abstract
The performance of very large scale integration (VLSI) circuits predominantly depends on routing of interconnected circuits. The major problems in the design of VLSI layouts are wire sizing, buffer sizing and buffer insertion. These are the techniques to improve power dissipation, area usage, noise and time delay. The interconnect delay can be optimized by choosing proper buffer locations along the routing path. A stochastic based Particle Swarm Optimization algorithm is used here to optimize buffer locations to find the shortest path and also simultaneously minimize the congestion. The performance is compared with Particle Swarm Optimization based VLSI routing. The results obtained shows the proposed approach has a good potential in VLSI routing and can be further extended in future.